Dual-clock edge sequential electronic circuits, or dual-clock edge registers such as the register A illustrated in FIG. 1, generally comprise a first D-type flip-flop 1, a second D-type flip-flop 2 and a multiplexer 3 sometimes referred to herein as a main multiplexer. The output of each of the two flip-flops 1 and 2 is coupled to a respective input of the main multiplexer.
A data signal D is delivered to a first input of the first flip-flop 1 and to a first input of the second flip-flop 2. The register A is gated by a clock signal CK. The clock signal CK is thus coupled to the clock signal input of each of the two flip-flops 1 and 2, as well as to the selection input of the main multiplexer 3. The selection input of a multiplexer corresponds to the input receiving the control signal which determines that signal, from among the two input signals, which is to be copied over to output.
The clock input of the second flip-flop 2 is an inverting input so that the second flip-flop 2 reacts on a clock falling edge while the first flip-flop, which does not possess an inverting clock input, reacts on a rising edge of the clock. Thus the register A operates in dual-clock edge fashion, that is to say it reacts both on a clock rising edge and on a clock falling edge.
Indeed, the first flip-flop 1 copies over, at its output, the value of the input signal, that is to say the data signal D, on a rising edge, while the second flip-flop 2 copies over at its output the value of the input signal, that is to say the data signal D, on a falling edge. The main multiplexer 3, as in a conventional dual-edge register, then receives at its inputs the output signals of the two flip-flops 1 and 2. The main multiplexer 3, also being gated by the clock signal CK, delivers at output Q the output signal of the first flip-flop 1 on a rising edge of the clock signal CK, and the output signal of the second flip-flop 2 on a falling edge. Indeed, on a rising edge of the clock signal, that is to say for a non-zero value of the clock signal, the output copies over the signal received at the first input, while on a clock falling edge, that is to say for a zero value of the clock signal, the output copies over the signal received on the second input of the main multiplexer 3.
Such dual-clock edge registers thus make it possible to double the passband with respect to a single-edge register, for one and the same clock frequency, thus making it possible to reduce the overall energy consumption. Note particularly, the consumption of a clock typically represents 30% of the energy consumption of an integrated circuit.
These sequential electronic circuits are difficult to test. Indeed, systems making it possible to test the proper operation of such circuits remain complex. The document US 2003/0218488 describes one method and system for checking the operation of a dual-clock edge register. However, in this document, to allow such a check, the system uses a second clock distinct from the clock used during normal operation. The use of two clocks then increases the energy consumption of the system.